1. Field of the Invention
This invention relates to superscalar microprocessors and more particularly to the alignment and dispatch of variable byte length computer instructions to a plurality of instruction decoders within a high performance and high frequency superscalar microprocessor.
2. Description of the Relevant Art
Superscalar microprocessors are capable of attaining performance characteristics which surpass those of conventional scalar processors by allowing the concurrent execution of multiple instructions. Due to the widespread acceptance of the x86 family of microprocessors, efforts have been undertaken by microprocessor manufacturers to develop superscalar microprocessors which execute x86 instructions. Such superscalar microprocessors achieve relatively high performance characteristics while advantageously maintaining backwards compatibility with the vast amount of existing software developed for previous microprocessor generations such as the 8086, 80286, 80386, and 80486.
The x86 instruction set is relatively complex and is characterized by a plurality of variable byte length instructions. A generic format illustrative of the x86 instruction set is shown in FIG. 1. As illustrated in the figure, an x86 instruction consists of from one to five optional prefix bytes 102, followed by an operation code (opcode) field 104, an optional addressing mode (Mod R/M) byte 106, an optional scale-index-base (SIB) byte 108, an optional displacement field 110, and an optional immediate data field 112.
The opcode field 104 defines the basic operation for a particular instruction. The default operation of a particular opcode may be modified by one or more prefix bytes. For example, a prefix byte may be used to change the address or operand size for an instruction, to override the default segment used in memory addressing, or to instruct the processor to repeat a string operation a number of times. The opcode field 104 follows the prefix bytes 102, if any, and may be one or two bytes in length. The addressing mode (Mod R/M) byte 106 specifies the registers used as well as memory addressing modes. The scale-index-base (SIB) byte 108 is used only in 32-bit base-relative addressing using scale and index factors. A base field of the SIB byte specifies which register contains the base value for the address calculation, and an index field specifies which register contains the index value. A scale field specifies the power of two by which the index value will be multiplied before being added, along with any displacement, to the base value. The next instruction field is the optional displacement field 110, which may be from one to four bytes in length. The displacement field 110 contains a constant used in address calculations. The optional immediate field 112, which may also be from one to four bytes in length, contains a constant used as an instruction operand. The shortest x86 instructions are only one byte long, and comprise a single opcode byte. The 80286 sets a maximum length for an instruction at 10 bytes, while the 80386 and 80486 both allow instruction lengths of up to 15 bytes.
The complexity of the x86 instruction set poses difficulties in implementing high performance x86 compatible superscalar microprocessors. One difficulty arises from the fact that instructions must be aligned with respect to the parallel-coupled instruction decoders of such processors before proper decode can be effectuated. In contrast to most RISC instruction formats, since the x86 instruction set consists of variable byte length instructions, the start bytes of successive instructions within a line are not necessarily equally spaced, and the number of instructions per line is not fixed. As a result, employment of simple, fixed-length shifting logic cannot in itself solve the problem of instruction alignment. Although scanning logic has been proposed to dynamically find the boundaries of instructions during the decode pipeline stage (or stages) of the processor, such a solution typically requires that the decode pipeline stage of the processor be implemented with a relatively large number of cascaded levels of logic gates and/or the allocation of several clock cycles to perform the scanning operation.
A further solution to instruction alignment and decode within x86 compatible superscalar microprocessors is described within the copending, commonly assigned patent application entitled xe2x80x9cSuperscalar Instruction Decoderxe2x80x9d, Ser. No. 08/146,383, filed Oct. 29, 1993 by Witt et al., the disclosure of which is incorporated herein by reference in its entirety. The solution proposed within the above-referenced patent application involves a translation of each variable length x86 instruction into one or more fixed-length RISC-like instructions. Upon translation, each fixed-length RISC-like instruction is aligned with respect to an allocated instruction decoder. While this solution has been quite successful, it too typically requires a relatively large number of cascaded levels of logic gates. This correspondingly limits the maximum overall clock frequency of the superscalar microprocessor.
The problems outlined above are in large part solved by a high performance superscalar microprocessor including an instruction alignment unit in accordance with the present invention. In one embodiment, an instruction alignment unit is provided which is capable of routing variable byte length instructions such as x86 instructions simultaneously to a plurality of decode units which form fixed issue positions within the superscalar microprocessor. The instruction alignment unit may be implemented with a relatively small number of cascaded levels of logic gates, thus accommodating very high frequencies of operation.
In one specific implementation, a superscalar microprocessor includes an instruction cache for storing a plurality of variable byte-length instructions and a predecode unit for generating predecode tags which identify the location of the start byte of each variable byte-length instruction. An instruction alignment unit is configured to channel a plurality of the variable byte-length instructions simultaneously to predetermined issue positions depending upon the locations of their corresponding start bytes in a cache line. The issue position or positions to which an instruction may be dispatched is limited depending upon the position of the instruction""s start byte within a line. By limiting the number of issue positions to which a given instruction of a line may be dispatched, the number of cascaded levels of logic required to implement the instruction alignment unit may be advantageously reduced.
In another implementation, instructions that have start bytes located at certain positions within a cache line may be restricted for dispatch to only one issue position, while instructions having start bytes at other positions within the cache line may be dispatched to one of a plurality of possible issue positions. By restricting the dispatch of those instructions having start bytes residing at certain positions within a line to a single issue position, the number of cascaded levels of logic may be reduced even further.
Broadly speaking, the invention contemplates an instruction alignment unit for routing a plurality of variable byte-length instructions from a stored line to a plurality of decode positions. The instruction alignment unit comprises a first multiplexer channel configured to route a first instruction having a corresponding start byte within a first range of byte locations of the line to a first decode position, and a second multiplexer channel configured to simultaneously route a second instruction having an associated start byte within a second range of byte locations of the line to a second decode position.
The invention further contemplates an instruction alignment unit for routing a plurality of variable byte-length instructions from a stored line to a plurality of decode positions, wherein the instruction alignment unit comprises a first multiplexer channel configured to route a first instruction having a corresponding start byte within a first range of byte locations of the line to a first decode position, a second multiplexer channel configured to simultaneously route a second instruction having an associated start byte within a second range of byte locations of the line to a second decode position, and a third multiplexer channel configured to route a third instruction having a corresponding start byte within a third range of locations within the line to a third decode position. A multiplexer control circuit is also coupled to said first, second, and third multiplexer channels, wherein the multiplexer control unit selectively controls each of the first, second, and third multiplexer channels in response to a predecode tag associated with each byte location of the line. The first and third ranges include a plurality of byte locations within the line while the second range is limited to a single byte location within said line.